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/**
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******************************************************************************
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* @file stm32h7xx_ll_cortex.h
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* @author MCD Application Team
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* @brief Header file of CORTEX LL module.
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The LL CORTEX driver contains a set of generic APIs that can be
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used by user:
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(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
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functions
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(+) Low power mode configuration (SCB register of Cortex-MCU)
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(+) MPU API to configure and enable regions
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(+) API to access to MCU info (CPUID register)
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(+) API to enable fault handler (SHCSR accesses)
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@endverbatim
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file in
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* the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H7xx_LL_CORTEX_H
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#define STM32H7xx_LL_CORTEX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx.h"
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/** @addtogroup STM32H7xx_LL_Driver
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* @{
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*/
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/** @defgroup CORTEX_LL CORTEX
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
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* @{
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*/
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/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
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* @{
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*/
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#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL /*!< AHB clock divided by 8 selected as SysTick clock source.*/
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#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
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* @{
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*/
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#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
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#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
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#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
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/**
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* @}
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*/
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#if __MPU_PRESENT
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/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
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* @{
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*/
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#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL /*!< Disable NMI and privileged SW access */
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#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
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#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
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#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
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* @{
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*/
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#define LL_MPU_REGION_NUMBER0 0x00UL /*!< REGION Number 0 */
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#define LL_MPU_REGION_NUMBER1 0x01UL /*!< REGION Number 1 */
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#define LL_MPU_REGION_NUMBER2 0x02UL /*!< REGION Number 2 */
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#define LL_MPU_REGION_NUMBER3 0x03UL /*!< REGION Number 3 */
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#define LL_MPU_REGION_NUMBER4 0x04UL /*!< REGION Number 4 */
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#define LL_MPU_REGION_NUMBER5 0x05UL /*!< REGION Number 5 */
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#define LL_MPU_REGION_NUMBER6 0x06UL /*!< REGION Number 6 */
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#define LL_MPU_REGION_NUMBER7 0x07UL /*!< REGION Number 7 */
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#if !defined(CORE_CM4)
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#define LL_MPU_REGION_NUMBER8 0x08UL /*!< REGION Number 8 */
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#define LL_MPU_REGION_NUMBER9 0x09UL /*!< REGION Number 9 */
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#define LL_MPU_REGION_NUMBER10 0x0AUL /*!< REGION Number 10 */
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#define LL_MPU_REGION_NUMBER11 0x0BUL /*!< REGION Number 11 */
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#define LL_MPU_REGION_NUMBER12 0x0CUL /*!< REGION Number 12 */
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#define LL_MPU_REGION_NUMBER13 0x0DUL /*!< REGION Number 13 */
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#define LL_MPU_REGION_NUMBER14 0x0EUL /*!< REGION Number 14 */
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#define LL_MPU_REGION_NUMBER15 0x0FUL /*!< REGION Number 15 */
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#endif /* !defined(CORE_CM4) */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
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* @{
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*/
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#define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
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#define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
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* @{
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*/
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#define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/
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#define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
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#define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
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#define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
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#define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
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#define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
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* @{
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*/
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#define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
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#define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
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#define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
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/* Legacy Define */
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#define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
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* @{
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*/
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#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL /*!< Instruction fetches enabled */
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#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
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* @{
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*/
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#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
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#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL /*!< Not Shareable memory attribute */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
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* @{
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*/
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#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
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#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL /*!< Not Cacheable memory attribute */
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/**
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* @}
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*/
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/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
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* @{
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*/
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#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
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#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL /*!< Not Bufferable memory attribute */
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/**
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* @}
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*/
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#endif /* __MPU_PRESENT */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
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* @{
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*/
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/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
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* @{
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*/
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/**
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* @brief This function checks if the Systick counter flag is active or not.
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* @note It can be used in timeout function on application side.
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* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
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{
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return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
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}
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/**
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* @brief Configures the SysTick clock source
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* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
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* @param Source This parameter can be one of the following values:
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
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{
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MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);
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}
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/**
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* @brief Get the SysTick clock source
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* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
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* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
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{
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return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));
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}
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/**
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* @brief Enable SysTick exception request
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
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{
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SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
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}
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/**
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* @brief Disable SysTick exception request
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
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* @retval None
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*/
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__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
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{
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CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
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}
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/**
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* @brief Checks if the SYSTICK interrupt is enabled or disabled.
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* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
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{
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return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
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}
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/**
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* @}
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||||
*/
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/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
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* @{
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*/
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||||
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||||
/**
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* @brief Processor uses sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
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* @retval None
|
||||
*/
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||||
__STATIC_INLINE void LL_LPM_EnableSleep(void)
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||||
{
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||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
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||||
}
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||||
|
||||
/**
|
||||
* @brief Processor uses deep sleep as its low power mode
|
||||
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
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||||
* @retval None
|
||||
*/
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||||
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
|
||||
{
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||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
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||||
SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
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||||
}
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||||
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||||
/**
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||||
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
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||||
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
|
||||
* empty main application.
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||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
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||||
* @retval None
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||||
*/
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||||
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
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||||
{
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||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
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||||
SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
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}
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||||
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||||
/**
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||||
* @brief Do not sleep when returning to Thread mode.
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||||
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
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||||
* @retval None
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||||
*/
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||||
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
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||||
{
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||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
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||||
CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);
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||||
}
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||||
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||||
/**
|
||||
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
|
||||
* processor.
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
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||||
* @retval None
|
||||
*/
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||||
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
|
||||
{
|
||||
/* Set SEVEONPEND bit of Cortex System Control Register */
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||||
SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
|
||||
}
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||||
|
||||
/**
|
||||
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
|
||||
* excluded
|
||||
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
|
||||
{
|
||||
/* Clear SEVEONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
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||||
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
|
||||
{
|
||||
/* Enable the system handler fault */
|
||||
SET_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a fault in System handler control register (SHCSR)
|
||||
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
|
||||
* @param Fault This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_HANDLER_FAULT_USG
|
||||
* @arg @ref LL_HANDLER_FAULT_BUS
|
||||
* @arg @ref LL_HANDLER_FAULT_MEM
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
|
||||
{
|
||||
/* Disable the system handler fault */
|
||||
CLEAR_BIT(SCB->SHCSR, Fault);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Implementer code
|
||||
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
|
||||
* @retval Value should be equal to 0x41 for ARM
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Variant number (The r value in the rnpn product revision identifier)
|
||||
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
|
||||
* @retval Value between 0 and 255 (0x0: revision 0)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Constant number
|
||||
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
|
||||
* @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Part number
|
||||
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
|
||||
* @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
|
||||
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
|
||||
* @retval Value between 0 and 255 (0x1: patch 1)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if __MPU_PRESENT
|
||||
/** @defgroup CORTEX_LL_EF_MPU MPU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable MPU with input options
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
|
||||
* @param Options This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
|
||||
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
|
||||
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
|
||||
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
|
||||
{
|
||||
/* Enable the MPU*/
|
||||
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
|
||||
/* Ensure MPU settings take effects */
|
||||
__DSB();
|
||||
/* Sequence instruction fetches using update settings */
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable MPU
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
/* Disable MPU*/
|
||||
WRITE_REG(MPU->CTRL, 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if MPU is enabled or not
|
||||
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
|
||||
{
|
||||
return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable a MPU region
|
||||
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @arg @ref LL_MPU_REGION_NUMBER8
|
||||
* @arg @ref LL_MPU_REGION_NUMBER9
|
||||
* @arg @ref LL_MPU_REGION_NUMBER10
|
||||
* @arg @ref LL_MPU_REGION_NUMBER11
|
||||
* @arg @ref LL_MPU_REGION_NUMBER12
|
||||
* @arg @ref LL_MPU_REGION_NUMBER13
|
||||
* @arg @ref LL_MPU_REGION_NUMBER14
|
||||
* @arg @ref LL_MPU_REGION_NUMBER15
|
||||
* @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Enable the MPU region */
|
||||
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure and enable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
|
||||
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR XN LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR AP LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR S LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR C LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR B LL_MPU_ConfigRegion\n
|
||||
* MPU_RASR SIZE LL_MPU_ConfigRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @arg @ref LL_MPU_REGION_NUMBER8
|
||||
* @arg @ref LL_MPU_REGION_NUMBER9
|
||||
* @arg @ref LL_MPU_REGION_NUMBER10
|
||||
* @arg @ref LL_MPU_REGION_NUMBER11
|
||||
* @arg @ref LL_MPU_REGION_NUMBER12
|
||||
* @arg @ref LL_MPU_REGION_NUMBER13
|
||||
* @arg @ref LL_MPU_REGION_NUMBER14
|
||||
* @arg @ref LL_MPU_REGION_NUMBER15
|
||||
* @param Address Value of region base address
|
||||
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
|
||||
* @param Attributes This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
|
||||
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
|
||||
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
|
||||
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
|
||||
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
|
||||
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
|
||||
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
|
||||
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
|
||||
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
|
||||
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
|
||||
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
|
||||
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
|
||||
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
|
||||
* @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Set base address */
|
||||
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
|
||||
/* Configure MPU */
|
||||
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a region
|
||||
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
|
||||
* MPU_RASR ENABLE LL_MPU_DisableRegion
|
||||
* @param Region This parameter can be one of the following values:
|
||||
* @arg @ref LL_MPU_REGION_NUMBER0
|
||||
* @arg @ref LL_MPU_REGION_NUMBER1
|
||||
* @arg @ref LL_MPU_REGION_NUMBER2
|
||||
* @arg @ref LL_MPU_REGION_NUMBER3
|
||||
* @arg @ref LL_MPU_REGION_NUMBER4
|
||||
* @arg @ref LL_MPU_REGION_NUMBER5
|
||||
* @arg @ref LL_MPU_REGION_NUMBER6
|
||||
* @arg @ref LL_MPU_REGION_NUMBER7
|
||||
* @arg @ref LL_MPU_REGION_NUMBER8
|
||||
* @arg @ref LL_MPU_REGION_NUMBER9
|
||||
* @arg @ref LL_MPU_REGION_NUMBER10
|
||||
* @arg @ref LL_MPU_REGION_NUMBER11
|
||||
* @arg @ref LL_MPU_REGION_NUMBER12
|
||||
* @arg @ref LL_MPU_REGION_NUMBER13
|
||||
* @arg @ref LL_MPU_REGION_NUMBER14
|
||||
* @arg @ref LL_MPU_REGION_NUMBER15
|
||||
* @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
|
||||
{
|
||||
/* Set Region number */
|
||||
WRITE_REG(MPU->RNR, Region);
|
||||
/* Disable the MPU region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_LL_CORTEX_H */
|
||||
|
||||
@@ -0,0 +1,780 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_ll_crs.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRS LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_LL_CRS_H
|
||||
#define STM32H7xx_LL_CRS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CRS)
|
||||
|
||||
/** @defgroup CRS_LL CRS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
|
||||
* @brief Flags defines which can be used with LL_CRS_ReadReg function
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
|
||||
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
|
||||
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
|
||||
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
|
||||
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
|
||||
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
|
||||
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_IT IT Defines
|
||||
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
|
||||
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
|
||||
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
|
||||
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
|
||||
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
|
||||
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
|
||||
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
|
||||
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
|
||||
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
|
||||
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
|
||||
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
|
||||
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
|
||||
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
|
||||
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
|
||||
* @{
|
||||
*/
|
||||
#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
|
||||
#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Reset value of the RELOAD field
|
||||
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
|
||||
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
|
||||
*/
|
||||
#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
|
||||
|
||||
/**
|
||||
* @brief Reset value of Frequency error limit.
|
||||
*/
|
||||
#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
|
||||
|
||||
/**
|
||||
* @brief Reset value of the HSI48 Calibration field
|
||||
* @note The default value is 64, which corresponds to the middle of the trimming interval.
|
||||
* The trimming step is specified in the product datasheet.
|
||||
* A higher TRIM value corresponds to a higher output frequency.
|
||||
*/
|
||||
#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in CRS register
|
||||
* @param __INSTANCE__ CRS Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in CRS register
|
||||
* @param __INSTANCE__ CRS Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
|
||||
* @note The RELOAD value should be selected according to the ratio between
|
||||
* the target frequency and the frequency of the synchronization source after
|
||||
* prescaling. It is then decreased by one in order to reach the expected
|
||||
* synchronization on the zero value. The formula is the following:
|
||||
* RELOAD = (fTARGET / fSYNC) -1
|
||||
* @param __FTARGET__ Target frequency (value in Hz)
|
||||
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
|
||||
* @retval Reload value (in Hz)
|
||||
*/
|
||||
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_Configuration Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable Frequency error counter
|
||||
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
|
||||
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_CEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Frequency error counter
|
||||
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Frequency error counter is enabled or not
|
||||
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Automatic trimming counter
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Automatic trimming counter
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Automatic trimming is enabled or not
|
||||
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set HSI48 oscillator smooth trimming
|
||||
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
|
||||
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 127
|
||||
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get HSI48 oscillator smooth trimming
|
||||
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
|
||||
* @retval a number between Min_Data = 0 and Max_Data = 127
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set counter reload value
|
||||
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
|
||||
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get counter reload value
|
||||
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
|
||||
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set frequency error limit
|
||||
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
|
||||
* @param Value a number between Min_Data = 0 and Max_Data = 255
|
||||
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get frequency error limit
|
||||
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
|
||||
* @retval A number between Min_Data = 0 and Max_Data = 255
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set division factor for SYNC signal
|
||||
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
|
||||
* @param Divider This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1
|
||||
* @arg @ref LL_CRS_SYNC_DIV_2
|
||||
* @arg @ref LL_CRS_SYNC_DIV_4
|
||||
* @arg @ref LL_CRS_SYNC_DIV_8
|
||||
* @arg @ref LL_CRS_SYNC_DIV_16
|
||||
* @arg @ref LL_CRS_SYNC_DIV_32
|
||||
* @arg @ref LL_CRS_SYNC_DIV_64
|
||||
* @arg @ref LL_CRS_SYNC_DIV_128
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get division factor for SYNC signal
|
||||
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1
|
||||
* @arg @ref LL_CRS_SYNC_DIV_2
|
||||
* @arg @ref LL_CRS_SYNC_DIV_4
|
||||
* @arg @ref LL_CRS_SYNC_DIV_8
|
||||
* @arg @ref LL_CRS_SYNC_DIV_16
|
||||
* @arg @ref LL_CRS_SYNC_DIV_32
|
||||
* @arg @ref LL_CRS_SYNC_DIV_64
|
||||
* @arg @ref LL_CRS_SYNC_DIV_128
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SYNC signal source
|
||||
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
|
||||
* @param Source This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_USB
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SYNC signal source
|
||||
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_USB
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set input polarity for the SYNC signal source
|
||||
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
|
||||
* @param Polarity This parameter can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
|
||||
{
|
||||
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get input polarity for the SYNC signal source
|
||||
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure CRS for the synchronization
|
||||
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
|
||||
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
|
||||
* CFGR FELIM LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
|
||||
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
|
||||
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
|
||||
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
|
||||
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
|
||||
* @param Settings This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
|
||||
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
|
||||
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
|
||||
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
|
||||
{
|
||||
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
|
||||
MODIFY_REG(CRS->CFGR,
|
||||
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
|
||||
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Generate software SYNC event
|
||||
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the frequency error direction latched in the time of the last
|
||||
* SYNC event
|
||||
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
|
||||
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the frequency error counter value latched in the time of the last SYNC event
|
||||
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
|
||||
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC event OK signal occurred or not
|
||||
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC warning signal occurred or not
|
||||
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Synchronization or trimming error signal occurred or not
|
||||
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Expected SYNC signal occurred or not
|
||||
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC error signal occurred or not
|
||||
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC missed error signal occurred or not
|
||||
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Trimming overflow or underflow occurred or not
|
||||
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the SYNC event OK flag
|
||||
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the SYNC warning flag
|
||||
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
|
||||
* the ERR flag
|
||||
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Expected SYNC flag
|
||||
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
|
||||
{
|
||||
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRS_LL_EF_IT_Management IT_Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable SYNC event OK interrupt
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SYNC event OK interrupt
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC event OK interrupt is enabled or not
|
||||
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable SYNC warning interrupt
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable SYNC warning interrupt
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if SYNC warning interrupt is enabled or not
|
||||
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Synchronization or trimming error interrupt
|
||||
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_ERRIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Synchronization or trimming error interrupt
|
||||
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Synchronization or trimming error interrupt is enabled or not
|
||||
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable Expected SYNC interrupt
|
||||
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
|
||||
{
|
||||
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Expected SYNC interrupt
|
||||
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
|
||||
{
|
||||
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if Expected SYNC interrupt is enabled or not
|
||||
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
|
||||
{
|
||||
return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_CRS_DeInit(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(CRS) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_LL_CRS_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,984 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_ll_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_LL_GPIO_H
|
||||
#define STM32H7xx_LL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
|
||||
|
||||
/** @defgroup GPIO_LL GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /*USE_FULL_LL_DRIVER*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LL GPIO Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_LL_EC_PIN */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_MODE.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
|
||||
|
||||
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
|
||||
|
||||
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_PULL.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
|
||||
|
||||
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
|
||||
This parameter can be a value of @ref GPIO_LL_EC_AF.
|
||||
|
||||
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
|
||||
} LL_GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_PIN PIN
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
|
||||
#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
|
||||
#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
|
||||
#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
|
||||
#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
|
||||
#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
|
||||
#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
|
||||
#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
|
||||
#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
|
||||
#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
|
||||
#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
|
||||
#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
|
||||
#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
|
||||
#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
|
||||
#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
|
||||
#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
|
||||
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \
|
||||
GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \
|
||||
GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \
|
||||
GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
|
||||
GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
|
||||
GPIO_BSRR_BS15) /*!< Select all pins */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_MODE Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
|
||||
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
|
||||
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
|
||||
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
|
||||
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_SPEED Output Speed
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
|
||||
#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
|
||||
#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
|
||||
#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
|
||||
|
||||
|
||||
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
|
||||
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
|
||||
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EC_AF Alternate Function
|
||||
* @{
|
||||
*/
|
||||
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
|
||||
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
|
||||
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
|
||||
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
|
||||
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
|
||||
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
|
||||
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
|
||||
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
|
||||
#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
|
||||
#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
|
||||
#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
|
||||
#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
|
||||
#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
|
||||
#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
|
||||
#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
|
||||
#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a value in GPIO register
|
||||
* @param __INSTANCE__ GPIO Instance
|
||||
* @param __REG__ Register to be written
|
||||
* @param __VALUE__ Value to be written in the register
|
||||
* @retval None
|
||||
*/
|
||||
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Read a value in GPIO register
|
||||
* @param __INSTANCE__ GPIO Instance
|
||||
* @param __REG__ Register to be read
|
||||
* @retval Register value
|
||||
*/
|
||||
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure gpio mode for a dedicated pin on dedicated port.
|
||||
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Mode This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_MODE_INPUT
|
||||
* @arg @ref LL_GPIO_MODE_OUTPUT
|
||||
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
||||
* @arg @ref LL_GPIO_MODE_ANALOG
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
|
||||
{
|
||||
MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio mode for a dedicated pin on dedicated port.
|
||||
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_MODE_INPUT
|
||||
* @arg @ref LL_GPIO_MODE_OUTPUT
|
||||
* @arg @ref LL_GPIO_MODE_ALTERNATE
|
||||
* @arg @ref LL_GPIO_MODE_ANALOG
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio output type for several pins on dedicated port.
|
||||
* @note Output type as to be set when gpio pin is in output or
|
||||
* alternate modes. Possible type are Push-pull or Open-drain.
|
||||
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @param OutputType This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
||||
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
|
||||
{
|
||||
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio output type for several pins on dedicated port.
|
||||
* @note Output type as to be set when gpio pin is in output or
|
||||
* alternate modes. Possible type are Push-pull or Open-drain.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
|
||||
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio speed for a dedicated pin on dedicated port.
|
||||
* @note I/O speed can be Low, Medium, Fast or High speed.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @note Refer to datasheet for frequency specifications and the power
|
||||
* supply and load conditions for each speed.
|
||||
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Speed This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
|
||||
{
|
||||
MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio speed for a dedicated pin on dedicated port.
|
||||
* @note I/O speed can be Low, Medium, Fast or High speed.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @note Refer to datasheet for frequency specifications and the power
|
||||
* supply and load conditions for each speed.
|
||||
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
|
||||
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Pull This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PULL_NO
|
||||
* @arg @ref LL_GPIO_PULL_UP
|
||||
* @arg @ref LL_GPIO_PULL_DOWN
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
|
||||
{
|
||||
MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PULL_NO
|
||||
* @arg @ref LL_GPIO_PULL_UP
|
||||
* @arg @ref LL_GPIO_PULL_DOWN
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF15 depending on target.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @param Alternate This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @arg @ref LL_GPIO_AF_8
|
||||
* @arg @ref LL_GPIO_AF_9
|
||||
* @arg @ref LL_GPIO_AF_10
|
||||
* @arg @ref LL_GPIO_AF_11
|
||||
* @arg @ref LL_GPIO_AF_12
|
||||
* @arg @ref LL_GPIO_AF_13
|
||||
* @arg @ref LL_GPIO_AF_14
|
||||
* @arg @ref LL_GPIO_AF_15
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
|
||||
{
|
||||
MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
|
||||
((((Pin * Pin) * Pin) * Pin) * Alternate));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
|
||||
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @arg @ref LL_GPIO_AF_8
|
||||
* @arg @ref LL_GPIO_AF_9
|
||||
* @arg @ref LL_GPIO_AF_10
|
||||
* @arg @ref LL_GPIO_AF_11
|
||||
* @arg @ref LL_GPIO_AF_12
|
||||
* @arg @ref LL_GPIO_AF_13
|
||||
* @arg @ref LL_GPIO_AF_14
|
||||
* @arg @ref LL_GPIO_AF_15
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->AFR[0],
|
||||
((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF15 depending on target.
|
||||
* @note Warning: only one pin can be passed as parameter.
|
||||
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @param Alternate This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @arg @ref LL_GPIO_AF_8
|
||||
* @arg @ref LL_GPIO_AF_9
|
||||
* @arg @ref LL_GPIO_AF_10
|
||||
* @arg @ref LL_GPIO_AF_11
|
||||
* @arg @ref LL_GPIO_AF_12
|
||||
* @arg @ref LL_GPIO_AF_13
|
||||
* @arg @ref LL_GPIO_AF_14
|
||||
* @arg @ref LL_GPIO_AF_15
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
|
||||
{
|
||||
MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
|
||||
(((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
|
||||
* @note Possible values are from AF0 to AF15 depending on target.
|
||||
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
|
||||
* @param GPIOx GPIO Port
|
||||
* @param Pin This parameter can be one of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_GPIO_AF_0
|
||||
* @arg @ref LL_GPIO_AF_1
|
||||
* @arg @ref LL_GPIO_AF_2
|
||||
* @arg @ref LL_GPIO_AF_3
|
||||
* @arg @ref LL_GPIO_AF_4
|
||||
* @arg @ref LL_GPIO_AF_5
|
||||
* @arg @ref LL_GPIO_AF_6
|
||||
* @arg @ref LL_GPIO_AF_7
|
||||
* @arg @ref LL_GPIO_AF_8
|
||||
* @arg @ref LL_GPIO_AF_9
|
||||
* @arg @ref LL_GPIO_AF_10
|
||||
* @arg @ref LL_GPIO_AF_11
|
||||
* @arg @ref LL_GPIO_AF_12
|
||||
* @arg @ref LL_GPIO_AF_13
|
||||
* @arg @ref LL_GPIO_AF_14
|
||||
* @arg @ref LL_GPIO_AF_15
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(GPIOx->AFR[1],
|
||||
(((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
|
||||
(Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Lock configuration of several pins for a dedicated port.
|
||||
* @note When the lock sequence has been applied on a port bit, the
|
||||
* value of this port bit can no longer be modified until the
|
||||
* next reset.
|
||||
* @note Each lock bit freezes a specific configuration register
|
||||
* (control and alternate function registers).
|
||||
* @rmtoll LCKR LCKK LL_GPIO_LockPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
__IO uint32_t temp;
|
||||
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
|
||||
WRITE_REG(GPIOx->LCKR, PinMask);
|
||||
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
|
||||
/* Read LCKK register. This read is mandatory to complete key lock sequence */
|
||||
temp = READ_REG(GPIOx->LCKR);
|
||||
(void) temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
|
||||
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
|
||||
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_LL_EF_Data_Access Data Access
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return full input data register value for a dedicated port.
|
||||
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval Input data register value of port
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(GPIOx->IDR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if input data level for several pins of dedicated port is high or low.
|
||||
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write output data register for the port.
|
||||
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PortValue Level value for each pin of the port
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
|
||||
{
|
||||
WRITE_REG(GPIOx->ODR, PortValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return full output data register value for a dedicated port.
|
||||
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval Output data register value of port
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return (uint32_t)(READ_REG(GPIOx->ODR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return if input data level for several pins of dedicated port is high or low.
|
||||
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set several pins to high level on dedicated gpio port.
|
||||
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->BSRR, PinMask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set several pins to low level on dedicated gpio port.
|
||||
* @rmtoll BSRR BRy LL_GPIO_ResetOutputPin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
WRITE_REG(GPIOx->BSRR, PinMask << 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle data value for several pin of dedicated port.
|
||||
* @rmtoll ODR ODy LL_GPIO_TogglePin
|
||||
* @param GPIOx GPIO Port
|
||||
* @param PinMask This parameter can be a combination of the following values:
|
||||
* @arg @ref LL_GPIO_PIN_0
|
||||
* @arg @ref LL_GPIO_PIN_1
|
||||
* @arg @ref LL_GPIO_PIN_2
|
||||
* @arg @ref LL_GPIO_PIN_3
|
||||
* @arg @ref LL_GPIO_PIN_4
|
||||
* @arg @ref LL_GPIO_PIN_5
|
||||
* @arg @ref LL_GPIO_PIN_6
|
||||
* @arg @ref LL_GPIO_PIN_7
|
||||
* @arg @ref LL_GPIO_PIN_8
|
||||
* @arg @ref LL_GPIO_PIN_9
|
||||
* @arg @ref LL_GPIO_PIN_10
|
||||
* @arg @ref LL_GPIO_PIN_11
|
||||
* @arg @ref LL_GPIO_PIN_12
|
||||
* @arg @ref LL_GPIO_PIN_13
|
||||
* @arg @ref LL_GPIO_PIN_14
|
||||
* @arg @ref LL_GPIO_PIN_15
|
||||
* @arg @ref LL_GPIO_PIN_ALL
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
|
||||
{
|
||||
uint32_t odr = READ_REG(GPIOx->ODR);
|
||||
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx);
|
||||
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_LL_GPIO_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,401 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_ll_utils.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of UTILS LL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file in
|
||||
* the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The LL UTILS driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) Device electronic signature
|
||||
(+) Timing functions
|
||||
(+) PLL configuration functions
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_LL_UTILS_H
|
||||
#define STM32H7xx_LL_UTILS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx.h"
|
||||
#include "stm32h7xx_ll_system.h"
|
||||
#include "stm32h7xx_ll_bus.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL UTILS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Max delay can be used in LL_mDelay */
|
||||
#define LL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
/**
|
||||
* @brief Unique device ID register base address
|
||||
*/
|
||||
#define UID_BASE_ADDRESS UID_BASE
|
||||
|
||||
/**
|
||||
* @brief Flash size data register base address
|
||||
*/
|
||||
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
|
||||
|
||||
/**
|
||||
* @brief Package data register base address
|
||||
*/
|
||||
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief UTILS PLL structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 63
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL1_SetM(). */
|
||||
|
||||
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
|
||||
This parameter must be a number between Min_Data = 4 and Max_Data = 512
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL1_SetN(). */
|
||||
|
||||
uint32_t PLLP; /*!< Division for the main system clock.
|
||||
This parameter must be a number between Min_Data = 2 and Max_Data = 128
|
||||
odd division factors are not allowed
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL1_SetP(). */
|
||||
|
||||
uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO.
|
||||
This parameter can be a value between 0 and 8191
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL1_SetFRACN(). */
|
||||
|
||||
uint32_t VCO_Input; /*!< PLL clock Input range.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL1_SetVCOInputRange(). */
|
||||
|
||||
uint32_t VCO_Output; /*!< PLL clock Output range.
|
||||
This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_PLL1_SetVCOOutputRange(). */
|
||||
|
||||
} LL_UTILS_PLLInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UTILS System, AHB and APB buses clock configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.
|
||||
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetSysPrescaler(). */
|
||||
|
||||
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAHBPrescaler(). */
|
||||
|
||||
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB1Prescaler(). */
|
||||
|
||||
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB2Prescaler(). */
|
||||
|
||||
uint32_t APB3CLKDivider; /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB3Prescaler(). */
|
||||
|
||||
uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
|
||||
This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
|
||||
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_RCC_SetAPB4Prescaler(). */
|
||||
|
||||
} LL_UTILS_ClkInitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
|
||||
* @{
|
||||
*/
|
||||
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
|
||||
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
|
||||
* @{
|
||||
*/
|
||||
#if (STM32H7_DEV_ID == 0x450UL)
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP100 LL_SYSCFG_LQFP100_PACKAGE /*!< LQFP100 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TQFP144 LL_SYSCFG_TQFP144_PACKAGE /*!< TQFP144 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176 LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240 LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */
|
||||
#elif (STM32H7_DEV_ID == 0x480UL)
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000UL /*!< LQFP64 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 0x00000001UL /*!< TFBGA100 or LQFP100 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x00000002UL /*!< LQFP100 with SMPS package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS 0x00000003UL /*!< TFBGA100 with SMPS package type */
|
||||
#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS 0x00000004UL /*!< WLCSP132 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000005UL /*!< LQFP144 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x00000006UL /*!< LQFP144 with SMPS package type */
|
||||
#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007UL /*!< UFBGA169 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 0x00000008UL /*!< UFBGA176 or LQFP176 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x00000009UL /*!< LQFP176 with SMPS package type */
|
||||
#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000AUL /*!< UFBGA176 with SMPS package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TFBGA216 0x0000000CUL /*!< TFBGA216 package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TFBGA225 0x0000000EUL /*!< TFBGA225 package type */
|
||||
#elif (STM32H7_DEV_ID == 0x483UL)
|
||||
#define LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS LL_SYSCFG_VFQFPN68_INDUS_PACKAGE /*!< VFQFPN68 Industrial package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 LL_SYSCFG_TFBGA100_LQFP100_PACKAGE /*!< TFBGA100 or LQFP100 Legacy package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP100_INDUS LL_SYSCFG_LQFP100_INDUS_PACKAGE /*!< LQFP100 Industrial package type */
|
||||
#define LL_UTILS_PACKAGETYPE_TFBGA100_INDUS LL_SYSCFG_TFBGA100_INDUS_PACKAGE /*!< TFBGA100 Industrial package type */
|
||||
#define LL_UTILS_PACKAGETYPE_WLCSP115_INDUS LL_SYSCFG_WLCSP115_INDUS_PACKAGE /*!< WLCSP115 Industrial package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP144 LL_SYSCFG_LQFP144_PACKAGE /*!< LQFP144 Legacy package type */
|
||||
#define LL_UTILS_PACKAGETYPE_UFBGA144 LL_SYSCFG_UFBGA144_PACKAGE /*!< UFBGA144 Legacy package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP144_INDUS LL_SYSCFG_LQFP144_INDUS_PACKAGE /*!< LQFP144 Industrial package type */
|
||||
#define LL_UTILS_PACKAGETYPE_UFBGA169_INDUS LL_SYSCFG_UFBGA169_INDUS_PACKAGE /*!< UFBGA169 Industrial package type */
|
||||
#define LL_UTILS_PACKAGETYPE_UFBGA176PLUS25_INDUS LL_SYSCFG_UFBGA176PLUS25_INDUS_PACKAGE /*!< UFBGA176+25 Industrial package type */
|
||||
#define LL_UTILS_PACKAGETYPE_LQFP176_INDUS LL_SYSCFG_LQFP176_INDUS_PACKAGE /*!< LQFP176 Industrial package type */
|
||||
#endif /* STM32H7_DEV_ID == 0x450UL */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[31:0]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[63:32]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
|
||||
* @retval UID[95:64]
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||
{
|
||||
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Flash memory size
|
||||
* @note This bitfield indicates the size of the device Flash memory expressed in
|
||||
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
|
||||
* @retval FLASH_SIZE[15:0]: Flash memory size
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
{
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Package type
|
||||
* @retval Returned value can be one of the following values:
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_TQFP144
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68_INDUS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_INDUS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_INDUS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP115_INDUS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_INDUS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_INDUS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176+25_INDUS (*)
|
||||
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_INDUS (*)
|
||||
*
|
||||
* (*) Packages available on some STM32H7 lines only.
|
||||
* @note For some SM32H7 lines, enabling the SYSCFG clock is mandatory.
|
||||
the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||
{
|
||||
#if defined(SYSCFG_PKGR_PKG)
|
||||
|
||||
return LL_SYSCFG_GetPackage();
|
||||
#else
|
||||
return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));
|
||||
|
||||
#endif /* SYSCFG_PKGR_PKG */
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_LL_EF_DELAY DELAY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function configures the Cortex-M SysTick source of the time base.
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Frequency of Ticks (Hz)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
{
|
||||
/* Configure the SysTick to have interrupt in 1ms time base */
|
||||
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||
}
|
||||
|
||||
void LL_Init1msTick(uint32_t CPU_Frequency);
|
||||
void LL_mDelay(uint32_t Delay);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup UTILS_EF_SYSTEM SYSTEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
void LL_SetSystemCoreClock(uint32_t CPU_Frequency);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
|
||||
uint32_t HSEBypass,
|
||||
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
|
||||
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
|
||||
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_LL_UTILS_H */
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
This software component is provided to you as part of a software package and
|
||||
applicable license terms are in the Package_license file. If you received this
|
||||
software component outside of a package or without applicable license terms,
|
||||
the terms of the BSD-3-Clause license shall apply.
|
||||
You may obtain a copy of the BSD-3-Clause at:
|
||||
https://opensource.org/licenses/BSD-3-Clause
|
||||
@@ -0,0 +1,456 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_ll_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_ll_exti.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32H7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (EXTI)
|
||||
|
||||
/** @defgroup EXTI_LL EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
|
||||
#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
|
||||
#define IS_LL_EXTI_LINE_64_95(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U)
|
||||
|
||||
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|
||||
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|
||||
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
|
||||
|
||||
|
||||
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|
||||
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup EXTI_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the EXTI registers to their default reset values.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: EXTI registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_EXTI_DeInit(void)
|
||||
{
|
||||
/* Rising Trigger selection register set to default reset values */
|
||||
LL_EXTI_WriteReg(RTSR1, 0x00000000U);
|
||||
LL_EXTI_WriteReg(RTSR2, 0x00000000U);
|
||||
LL_EXTI_WriteReg(RTSR3, 0x00000000U);
|
||||
|
||||
/* Falling Trigger selection register set to default reset values */
|
||||
LL_EXTI_WriteReg(FTSR1, 0x00000000U);
|
||||
LL_EXTI_WriteReg(FTSR2, 0x00000000U);
|
||||
LL_EXTI_WriteReg(FTSR3, 0x00000000U);
|
||||
|
||||
/* Software interrupt event register set to default reset values */
|
||||
LL_EXTI_WriteReg(SWIER1, 0x00000000U);
|
||||
LL_EXTI_WriteReg(SWIER2, 0x00000000U);
|
||||
LL_EXTI_WriteReg(SWIER3, 0x00000000U);
|
||||
|
||||
/* D3 Pending register set to default reset values */
|
||||
LL_EXTI_WriteReg(D3PMR1, 0x00000000U);
|
||||
LL_EXTI_WriteReg(D3PMR2, 0x00000000U);
|
||||
LL_EXTI_WriteReg(D3PMR3, 0x00000000U);
|
||||
|
||||
/* D3 Pending clear selection register low to default reset values */
|
||||
LL_EXTI_WriteReg(D3PCR1L, 0x00000000U);
|
||||
LL_EXTI_WriteReg(D3PCR2L, 0x00000000U);
|
||||
LL_EXTI_WriteReg(D3PCR3L, 0x00000000U);
|
||||
|
||||
/* D3 Pending clear selection register high to default reset values */
|
||||
LL_EXTI_WriteReg(D3PCR1H, 0x00000000U);
|
||||
LL_EXTI_WriteReg(D3PCR2H, 0x00000000U);
|
||||
LL_EXTI_WriteReg(D3PCR3H, 0x00000000U);
|
||||
|
||||
/* Interrupt mask register reset */
|
||||
LL_EXTI_WriteReg(IMR1, 0x00000000U);
|
||||
LL_EXTI_WriteReg(IMR2, 0x00000000U);
|
||||
LL_EXTI_WriteReg(IMR3, 0x00000000U);
|
||||
|
||||
/* Event mask register reset */
|
||||
LL_EXTI_WriteReg(EMR1, 0x00000000U);
|
||||
LL_EXTI_WriteReg(EMR2, 0x00000000U);
|
||||
LL_EXTI_WriteReg(EMR3, 0x00000000U);
|
||||
|
||||
/* Clear Pending requests */
|
||||
LL_EXTI_WriteReg(PR1, EXTI_PR1_PR_Msk);
|
||||
LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk);
|
||||
LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk);
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/* Interrupt mask register set to default reset values for Core 2 (Coretx-M4)*/
|
||||
LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
|
||||
LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
|
||||
LL_EXTI_WriteReg(C2IMR3, 0x00000000U);
|
||||
|
||||
/* Event mask register set to default reset values */
|
||||
LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
|
||||
LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
|
||||
LL_EXTI_WriteReg(C2EMR3, 0x00000000U);
|
||||
|
||||
/* Clear Pending requests */
|
||||
LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk);
|
||||
LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk);
|
||||
LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk);
|
||||
|
||||
#endif /* DUAL_CORE*/
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: EXTI registers are initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
|
||||
assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63));
|
||||
assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
|
||||
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
|
||||
|
||||
/* ENABLE LineCommand */
|
||||
if (EXTI_InitStruct->LineCommand != DISABLE)
|
||||
{
|
||||
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
|
||||
|
||||
/* Configure EXTI Lines in range from 0 to 31 */
|
||||
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
|
||||
{
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
|
||||
{
|
||||
/* Enable IT on provided Lines for Cortex-M7*/
|
||||
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable IT on provided Lines for Cortex-M7*/
|
||||
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
|
||||
{
|
||||
/* Enable event on provided Lines for Cortex-M7 */
|
||||
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable event on provided Lines for Cortex-M7 */
|
||||
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
#if defined(DUAL_CORE)
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
|
||||
{
|
||||
/* Enable IT on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable IT on provided Lines for Cortex-M4*/
|
||||
LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
|
||||
{
|
||||
/* Enable event on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable event on provided Lines for Cortex-M4*/
|
||||
LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
}
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
|
||||
{
|
||||
switch (EXTI_InitStruct->Trigger)
|
||||
{
|
||||
case LL_EXTI_TRIGGER_RISING:
|
||||
/* First Disable Falling Trigger on provided Lines */
|
||||
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable Rising Trigger on provided Lines */
|
||||
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_FALLING:
|
||||
/* First Disable Rising Trigger on provided Lines */
|
||||
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
/* Then Enable Falling Trigger on provided Lines */
|
||||
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_RISING_FALLING:
|
||||
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
|
||||
break;
|
||||
default:
|
||||
status = ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Configure EXTI Lines in range from 32 to 63 */
|
||||
if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE)
|
||||
{
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
|
||||
{
|
||||
/* Enable IT on provided Lines for Cortex-M7*/
|
||||
LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable IT on provided Lines for Cortex-M7*/
|
||||
LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
|
||||
}
|
||||
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
|
||||
{
|
||||
/* Enable event on provided Lines for Cortex-M7 */
|
||||
LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable event on provided Lines for Cortex-M7 */
|
||||
LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
|
||||
}
|
||||
#if defined(DUAL_CORE)
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
|
||||
{
|
||||
/* Enable IT on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable IT on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63);
|
||||
}
|
||||
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
|
||||
{
|
||||
/* Enable event on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable event on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
|
||||
}
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
|
||||
{
|
||||
switch (EXTI_InitStruct->Trigger)
|
||||
{
|
||||
case LL_EXTI_TRIGGER_RISING:
|
||||
/* First Disable Falling Trigger on provided Lines */
|
||||
LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
|
||||
/* Then Enable IT on provided Lines */
|
||||
LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_FALLING:
|
||||
/* First Disable Rising Trigger on provided Lines */
|
||||
LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
|
||||
/* Then Enable Falling Trigger on provided Lines */
|
||||
LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_RISING_FALLING:
|
||||
LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63);
|
||||
LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63);
|
||||
break;
|
||||
default:
|
||||
status = ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Configure EXTI Lines in range from 64 to 95 */
|
||||
if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE)
|
||||
{
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT)
|
||||
{
|
||||
/* Enable IT on provided Lines for Cortex-M7*/
|
||||
LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable IT on provided Lines for Cortex-M7*/
|
||||
LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
|
||||
}
|
||||
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT)
|
||||
{
|
||||
/* Enable event on provided Lines for Cortex-M7 */
|
||||
LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable event on provided Lines for Cortex-M7 */
|
||||
LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
|
||||
}
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
|
||||
{
|
||||
/* Enable IT on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable IT on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95);
|
||||
}
|
||||
|
||||
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
|
||||
{
|
||||
/* Enable event on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable event on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
|
||||
}
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
|
||||
{
|
||||
switch (EXTI_InitStruct->Trigger)
|
||||
{
|
||||
case LL_EXTI_TRIGGER_RISING:
|
||||
/* First Disable Falling Trigger on provided Lines */
|
||||
LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
|
||||
/* Then Enable IT on provided Lines */
|
||||
LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_FALLING:
|
||||
/* First Disable Rising Trigger on provided Lines */
|
||||
LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
|
||||
/* Then Enable Falling Trigger on provided Lines */
|
||||
LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
|
||||
break;
|
||||
case LL_EXTI_TRIGGER_RISING_FALLING:
|
||||
LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95);
|
||||
LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95);
|
||||
break;
|
||||
default:
|
||||
status = ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else /* DISABLE LineCommand */
|
||||
{
|
||||
/* Disable IT on provided Lines for Cortex-M7*/
|
||||
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
|
||||
LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
|
||||
|
||||
/* Disable event on provided Lines for Cortex-M7 */
|
||||
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
|
||||
LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
|
||||
|
||||
#if defined(DUAL_CORE)
|
||||
/* Disable IT on provided Lines for Cortex-M4*/
|
||||
LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
|
||||
LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
|
||||
|
||||
/* Disable event on provided Lines for Cortex-M4 */
|
||||
LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
|
||||
LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
|
||||
LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
|
||||
#endif /* DUAL_CORE */
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
|
||||
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
|
||||
EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE;
|
||||
EXTI_InitStruct->Line_64_95 = LL_EXTI_LINE_NONE;
|
||||
EXTI_InitStruct->LineCommand = DISABLE;
|
||||
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
|
||||
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (EXTI) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
@@ -0,0 +1,305 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_ll_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_ll_gpio.h"
|
||||
#include "stm32h7xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32H7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
|
||||
|
||||
/** @addtogroup GPIO_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
|
||||
|
||||
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
|
||||
((__VALUE__) == LL_GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
|
||||
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
|
||||
|
||||
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
|
||||
((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
|
||||
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
|
||||
((__VALUE__) == LL_GPIO_PULL_UP) ||\
|
||||
((__VALUE__) == LL_GPIO_PULL_DOWN))
|
||||
|
||||
#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_1 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_2 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_3 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_4 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_5 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_6 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_7 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_8 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_9 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_10 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_11 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_12 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_13 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_14 ) ||\
|
||||
((__VALUE__) == LL_GPIO_AF_15 ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize GPIO registers (Registers restored to their default values).
|
||||
* @param GPIOx GPIO Port
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: GPIO registers are de-initialized
|
||||
* - ERROR: Wrong GPIO Port
|
||||
*/
|
||||
ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
|
||||
/* Force and Release reset on clock of GPIOx Port */
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOA);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOA);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOB);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOB);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOC);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOC);
|
||||
}
|
||||
#if defined(GPIOD)
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOD);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOD);
|
||||
}
|
||||
#endif /* GPIOD */
|
||||
#if defined(GPIOE)
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOE);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOE);
|
||||
}
|
||||
#endif /* GPIOE */
|
||||
#if defined(GPIOF)
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOF);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOF);
|
||||
}
|
||||
#endif /* GPIOF */
|
||||
#if defined(GPIOG)
|
||||
else if (GPIOx == GPIOG)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOG);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOG);
|
||||
}
|
||||
#endif /* GPIOG */
|
||||
#if defined(GPIOH)
|
||||
else if (GPIOx == GPIOH)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOH);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOH);
|
||||
}
|
||||
#endif /* GPIOH */
|
||||
#if defined(GPIOI)
|
||||
else if (GPIOx == GPIOI)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOI);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOI);
|
||||
}
|
||||
#endif /* GPIOI */
|
||||
#if defined(GPIOJ)
|
||||
else if (GPIOx == GPIOJ)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOJ);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOJ);
|
||||
}
|
||||
#endif /* GPIOJ */
|
||||
#if defined(GPIOK)
|
||||
else if (GPIOx == GPIOK)
|
||||
{
|
||||
LL_AHB4_GRP1_ForceReset(LL_AHB4_GRP1_PERIPH_GPIOK);
|
||||
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_GPIOK);
|
||||
}
|
||||
#endif /* GPIOK */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
|
||||
* @param GPIOx GPIO Port
|
||||
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
|
||||
* that contains the configuration information for the specified GPIO peripheral.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
|
||||
* - ERROR: Not applicable
|
||||
*/
|
||||
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos, currentpin;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
|
||||
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
|
||||
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
|
||||
|
||||
/* ------------------------- Configure the port pins ---------------- */
|
||||
/* Initialize pinpos on first pin set */
|
||||
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
|
||||
{
|
||||
/* Get current io position */
|
||||
currentpin = (GPIO_InitStruct->Pin) & (0x00000001UL << pinpos);
|
||||
|
||||
if (currentpin != 0x00000000U)
|
||||
{
|
||||
|
||||
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
|
||||
|
||||
/* Output mode configuration*/
|
||||
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
|
||||
|
||||
}
|
||||
|
||||
/* Pull-up Pull down resistor configuration*/
|
||||
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
|
||||
|
||||
if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
|
||||
{
|
||||
/* Check Alternate parameter */
|
||||
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
|
||||
|
||||
/* Alternate function configuration */
|
||||
if (currentpin < LL_GPIO_PIN_8)
|
||||
{
|
||||
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
|
||||
}
|
||||
}
|
||||
|
||||
/* Pin Mode configuration */
|
||||
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
|
||||
}
|
||||
pinpos++;
|
||||
}
|
||||
|
||||
return (SUCCESS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
|
||||
* @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
|
||||
GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
|
||||
GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
|
||||
GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
|
||||
@@ -0,0 +1,84 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_ll_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#if defined (USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_ll_pwr.h"
|
||||
|
||||
/** @addtogroup STM32H7xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (PWR)
|
||||
|
||||
/** @defgroup PWR_LL PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWR_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize the PWR registers to their default reset values.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: PWR registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_PWR_DeInit(void)
|
||||
{
|
||||
#if defined (PWR_WKUPCR_WKUPC3)
|
||||
WRITE_REG(PWR->WKUPCR, (PWR_WKUPCR_WKUPC1 | PWR_WKUPCR_WKUPC2 | PWR_WKUPCR_WKUPC3 | \
|
||||
PWR_WKUPCR_WKUPC4 | PWR_WKUPCR_WKUPC5 | PWR_WKUPCR_WKUPC6));
|
||||
#else
|
||||
WRITE_REG(PWR->WKUPCR, (PWR_WKUPCR_WKUPC1 | PWR_WKUPCR_WKUPC2 | \
|
||||
PWR_WKUPCR_WKUPC4 | PWR_WKUPCR_WKUPC6));
|
||||
#endif /* defined (PWR_WKUPCR_WKUPC3) */
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (PWR) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined (USE_FULL_LL_DRIVER) */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user